What you've learned

You should now know how to:

  • Describe common cache PMU events.
  • Describe why some code triggers PMU events on the Neoverse N2 core.
  • Describe the events triggered during common scenarios.

Knowledge Check

Some PMU events do not occur on the Neoverse CPUs if they are not provided by a system component.

Which of the following events always occur during an L2 D-cache access from a load instruction?

What scenario does not trigger L1D_CACHE_WB in a Neoverse N2 core?

Why do I-side cache refills typically count less than D-side cache refills?