Some PMU events do not occur on the Neoverse CPUs if they are not provided by a system component.
Events like LL_CACHE_RD count transactions returned from outside of the Neoverse N2 CPU.
Which of the following events always occur during an L2 D-cache access from a load instruction?
L2D_CACHE_RD counts an L2 D-cache access caused by a load or read. A refill and bus access only occurs when there is a miss. L2D_CACHE_WR is only counted when an L2 D-cache access is caused by a store or write.
L1D_CACHE_WB counts any writeback of dirty data from the L1 D-cache to the L2 cache, including writebacks from snoops, CMOs or evictions. Writing directly to the L2 cache, such as in write-streaming mode, will not result in a writeback from the L1 D-cache to the L2. L1D_CACHE_WB is Implementation Defined whether the event counts for
In the Neoverse N2, instruction fetches that miss in the I-cache will look in the D-cache and the L2 cache.