About this Learning Path

Who is this for?

This is an advanced topic for software and hardware engineers who want to learn about the causes of common Neoverse cache Performance Monitoring Unit (PMU) events.

What will you learn?

Upon completion of this learning path, you will be able to:

  • Describe common cache PMU events.
  • Describe why some code triggers PMU events on the Neoverse N2 core.
  • Describe the events triggered during common scenarios.


Before starting, you will need the following:

  • Knowledge of performance analysis.
  • The ability to read Arm assembly code.