Learn about Neoverse Cache PMU Events using C and Assembly Language
Introduction
Introduction to the PMU
L1 Data Cache Events
L1 Instruction Cache Events
L2 Unified Cache Events
LL Cache Events
Next Steps
Learn about Neoverse Cache PMU Events using C and Assembly Language
Who is this for?
This is an advanced topic for software and hardware engineers who want to learn about the causes of common Neoverse cache Performance Monitoring Unit (PMU) events.
What will you learn?
After completing this Learning Path, you'll be able to perform the following tasks:
- Describe common cache PMU events.
- Describe why some code triggers PMU events on the Neoverse N2 core.
- Describe the events triggered during common scenarios.
Prerequisites
Before starting, you'll need the following prerequisites:
- Knowledge of performance analysis.
- The ability to read Arm assembly code.