Learn about Neoverse Non-cache PMU events using C and Assembly Language: Review

Learn about Neoverse Non-cache PMU events using C and Assembly Language

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Learn about Neoverse Non-cache PMU events using C and Assembly Language

What you've learned

You should now know how to:

Describe common non-cache PMU events.
Understand why specific code triggers specific PMU events on the Neoverse N2 Core.

Knowledge Check

ITLB_WALK counts page table walks as a result of TLB maintenance operations.

true

false

ASE_SPEC differs from ASE_INST_SPEC because ASE_SPEC only counts speculatively executed Advanced SIMD operations, excluding load, store, and move micro-operations.

true

false

Which of the following is true?

Speculatively executed PMU event counts are always greater than or equal to retired PMU event counts.

Speculatively executed PMU events count architecturally executed operations or instructions.

Speculatively executed PMU event counts are always less than retired PMU event counts.

Speculatively executed PMU event counts and retired PMU event counts can be higher, lower or equal to each other.

Which of these scenarios trigger an ITLB walk?

A memory access driven by an instruction.

An instruction Cache Maintenance Operation.

A translation fault.

An instruction-side memory translation that has not been accessed before.

Back

Learn about Neoverse Non-cache PMU events using C and Assembly Language

Introduction

Introduction to the PMU

Topdown Methodology L1 Events

TLB Events

Operation Mix Events

Review

Next Steps

Learn about Neoverse Non-cache PMU events using C and Assembly Language

What you've learned

Knowledge Check