Optimize memory access behavior using Arm Performix and the Arm MCP Server

Who is this for?

This is an introductory topic for C++ developers who want to use Arm Performix and the Arm MCP Server to diagnose cache and address translation behavior in applications running on Arm Neoverse servers.

What will you learn?

Upon completion of this Learning Path, you will be able to:

• Explain how L1 cache hits, TLB misses, and page walks affect C++ application performance.
• Build and visualize the orbiting galaxies example on an Arm Neoverse server.
• Inspect and optimize the particle data structure using insights from the memory access recipe.
• Use the Arm MCP Server in combination with Arm Performix for an agentic solution.

Prerequisites

Before starting, you will need the following:

• Access to an Arm Neoverse bare metal server.
• Basic understanding of memory hierarchy within a CPU.
• Basic C++ development experience.
• Familiarity with the Linux command line.