# [Optimize memory access behavior using Arm Performix and the Arm MCP Server](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/)

## In this learning path

- [Introduction](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/)
- [Understand CPU memory hierarchy and address translation](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/how-to-0/)
- [Set up and build the example application](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/how-to-1/)
- [Profile memory access behavior with Arm Performix](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/how-to-2/)
- [Optimize the application manually and with the Arm MCP Server](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/how-to-3/)
- [Next Steps](https://learn.arm.com/learning-paths/servers-and-cloud-computing/performix-memory-access/_next-steps/)

## About this Learning Path

|               |                         |
|---------------|-------------------------|
| Skill level:  | Introductory            |
| Reading time: | 45 min                  |
| Last updated: | 31 Jul 2026             |

| Author:                | Kieran Hejmadi, Arm [[GitHub](https://github.com/kieranhejmadi01)] [[LinkedIn](https://linkedin.com/in/kieran-hejmadi-88920815b)] |
|------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------|
| Arm IP:                | [Neoverse](https://support.arm.com/?tab=compute-ip&Product%20Type=Infrastructure%20Processors)                                                                                  |
| Tags:                  | [Performance and Architecture](https://learn.arm.com/tag/performance-and-architecture), [Linux](https://learn.arm.com/tag/linux), [Arm Performix](https://learn.arm.com/tag/arm-performix), [MCP](https://learn.arm.com/tag/mcp), [CPP](https://learn.arm.com/tag/cpp), [CMake](https://learn.arm.com/tag/cmake), [Python](https://learn.arm.com/tag/python), [perf](https://learn.arm.com/tag/perf) |

### Who is this for?
This is an introductory topic for C++ developers who want to use Arm Performix and the Arm MCP Server to diagnose cache and address translation behavior in applications running on Arm Neoverse servers.

### What will you learn?
Upon completion of this Learning Path, you will be able to:
- Explain how L1 cache hits, TLB misses, and page walks affect C++ application performance.
- Build and visualize the orbiting galaxies example on an Arm Neoverse server.
- Inspect and optimize the particle data structure using insights from the memory access recipe.
- Use the Arm MCP Server in combination with Arm Performix for an agentic solution.

### Prerequisites
Before starting, you will need the following:
- Access to an Arm Neoverse bare metal server.
- Basic understanding of memory hierarchy within a CPU.
- Basic C++ development experience.
- Familiarity with the Linux command line.