Who is this for?

This is an introductory topic for software developers interested in System on Chip Design.

What will you learn?

Upon completion of this Learning Path, you will be able to:

  • Configure and integrate an AXI-Lite peripheral with a Cortex-A9 Processing System.
  • Program the Cortex-A9 processor to read the state of switches and control the LEDs using a C program.
  • Demonstrate a basic functional system that lights up the LEDs based on the status of the switches.

Prerequisites

Before starting, you will need the following:

  • Some familiarity with Verilog
  • Basic understanding of System on Chip design
  • A ‘Zybo Z7-10’ development board

Summary

AI-assisted

This summary was drafted with an approved AI-assisted workflow and reviewed by Arm contributors before publication. Human technical review remains part of the process so the final page reflects engineering rigor, accuracy, and Arm editorial standards.

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You’ll design and integrate a custom AXI4-Lite peripheral with the ZYNQ Processing System on a Zybo Z7-10 board. First, you’ll create a clean Vivado workspace. Then, you’ll follow the Create and Package New IP flow to build the peripheral, and add external ports for LEDs and switches with the shown bit widths. You’ll create a block design that connects the peripheral to the Cortex-A9–based processing system, followed by generating an HDL wrapper and a bitstream. Using Vitis IDE, you’ll write a bare-metal C program that reads switch inputs over AXI-Lite and drives LED outputs. You’ll see LEDs responding to switch states through the custom IP.

Frequently asked questions

AI-assisted

These FAQs were drafted with an approved AI-assisted workflow and reviewed by Arm contributors before publication. Human technical review remains part of the process so the final page reflects engineering rigor, accuracy, and Arm editorial standards.

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What should I check about the Vivado workspace path before creating the project?
Use a path with no spaces. A simple top-level directory such as C:/Workspace avoids path issues.
Which option should I select in the **Create and Package New IP** wizard?
Select Create a new AXI4 peripheral. This generates the template files for an AXI-compliant custom IP block.
How do I know the `led` and `sw` ports are configured correctly?
Confirm led is an output and sw is an input, each with the width shown in the steps (four bits). They should appear as external ports in the block design and connect to your custom peripheral.
What should I do before generating the bitstream?
Create the HDL wrapper for design1.bd using the default options and save all changes. Then proceed to generate the bitstream.
What result should I expect when I run the C application in Vitis?
The LEDs change based on the state of the switches. Toggling a switch updates the corresponding LED as defined by your application.
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