# Debug Safety Island code

## In this learning path

- [Introduction](https://learn.arm.com/learning-paths/automotive/zenacssdebug/)
- [Getting started](https://learn.arm.com/learning-paths/automotive/zenacssdebug/zena/)
- [Launch the FVP](https://learn.arm.com/learning-paths/automotive/zenacssdebug/launch/)
- [Configure the model](https://learn.arm.com/learning-paths/automotive/zenacssdebug/config/)
- [Create debug connections](https://learn.arm.com/learning-paths/automotive/zenacssdebug/connect/)
- [Debug RSE from reset](https://learn.arm.com/learning-paths/automotive/zenacssdebug/rse/)
- [Debug Safety Island code](https://learn.arm.com/learning-paths/automotive/zenacssdebug/safetyisland/)
- [Debug primary compute and Linux](https://learn.arm.com/learning-paths/automotive/zenacssdebug/primarycompute/)
- [Next Steps](https://learn.arm.com/learning-paths/automotive/zenacssdebug/_next-steps/)

## Debug Safety Island code from beginning
The Safety Island subsystem based on the Cortex-R82AE is released from reset by RSE code. To debug Safety Island from first instruction, you must let the RSE (Cortex‑M55) code reach the point where it enables Safety Island on the Zena CSS FVP.

## Launch the FVP and reconnect RSE
If necessary, start (or restart) the FVP held at reset and reconnect the RSE model connection in Arm Development Studio:

```
kas shell -c "../layers/meta-arm/scripts/runfvp -t tmux --verbose -- --iris-server --iris-port 7100"
```

<div>
For remote debugging, add `-A` and ensure the chosen Iris port (default `7100`) is reachable.
</div>

## Connect the debugger to Safety Island (Cortex-R82AE)
Configure the **SI** model connection similarly to **RSE**. Add the following **Debugger commands** to load symbols, set up source path substitution, and break at the Safety Island reset entry (`arch_exception_reset`):

```
stop
add-symbol-file "/arm-auto-solutions/build/tmp_baremetal/deploy/images/fvp-rd-aspen/si0_ramfw.elf"
set substitute-path "/usr/src/debug/scp-firmware/2.16.0+git/" "/arm-auto-solutions/build/tmp_baremetal/work/fvp_rd_aspen-poky-linux/scp-firmware/2.16.0+git/git/"
b arch_exception_reset
```

<div>
Paths vary by environment. Use your actual build output and source locations when adding symbols or configuring path substitution.
</div>

## Start execution to release Safety Island
In **Debug Control**, select the **RSE** connection and start execution (run). The **SI** connection remains unavailable to run until Safety Island is powered up.

When RSE enables Safety Island, you will see a log message like:

```
__output__[INF] BL2: SI CL0 post load start
```

## Full output log
The full output log is shown here for your reference:

```
__output__[INF] [CC3XX] Init OK PIDR0: 0xc1
__output__[INF] Starting TF-M BL1_1
__output__[INF] Jumping to BL1_2
__output__[INF] Starting TF-M BL1_2
__output__[INF] Attempting to boot image 0
__output__[INF] BL2 image decrypted successfully
__output__[INF] BL2 image validated successfully
__output__[INF] Jumping to BL2
__output__[INF] Starting bootloader
__output__[INF] [CC3XX] Init OK PIDR0: 0xc1
__output__[INF] PSA Crypto init done, sig_type: EC-P256
__output__[INF] BL2: SI CL1 not present, skip loading
__output__[INF] BL2: SI CL0 pre load start
__output__[INF] BL2: SI CL0 pre load complete
__output__[INF] Primary   slot: version=0.0.7+0
__output__[INF] Image 3 Secondary slot: Image not found
__output__[INF] Image 3 RAM loading to 0x70083c00 is succeeded.
__output__[INF] Key 0 hash found for image 3
__output__[INF] Image 3 loaded from the primary slot
__output__[INF] BL2: SI CL0 post load start
__output__[INF] BL2: SI ATU region 0: [0x80000000 - 0xbfffffff]->[0x1_00000000 - 0x1_3fffffff]
__output__[INF] BL2: SI ATU region 1: [0xc0000000 - 0xcfffffff]->[0x1_40000000 - 0x1_4fffffff]
__output__[INF] BL2: SI ATU region 2: [0xd0000000 - 0xd001ffff]->[0x20000_d8000000 - 0x20000_d801ffff]
__output__[INF] BL2: SI ATU region 3: [0xd0020000 - 0xd002ffff]->[0x20000_d0200000 - 0x20000_d020ffff]
__output__[INF] BL2: SI ATU region 4: [0xd0030000 - 0xd003ffff]->[0x20000_d0400000 - 0x20000_d040ffff]
__output__[INF] BL2: SI ATU region 5: [0xd0040000 - 0xd006ffff]->[0x20000_d0100000 - 0x20000_d012ffff]
__output__[INF] BL2: SI ATU region 6: [0xe0030000 - 0xe0031fff]->[0x0_00000000 - 0x0_00001fff]
__output__[INF] BL2: SI ATU region 7: [0xe0130000 - 0xe0135fff]->[0x0_00100000 - 0x0_00105fff]
```